entity serial_handler is
	port(
		clk : in std_logic;
		nrst : in std_logic;
		data_in : in std_logic;
		data_out : out std_logic;
		dtr : in std_logic;
		txd : out std_logic;
		rxd : in std_logic
	);
end entity serial_handler;
architecture serial_dtr of serial_handler is
begin
	p1 : process (clk )
	begin
		if  rising_edge(clk) then
			if dtr = ‘0’ then
				data_out <= rxd;
			end if;
			txd <= data_in;
		end if;
	end process p1;
end architecture basic;