library ieee;
use ieee.std_logic_1164.all;
use work.processor_functions.all;
entity memory is
	port (
		clk : in std_logic;
		nrst : in std_logic;
		mdr_load : in std_logic;
		mar_load : in std_logic;
		mar_valid : in std_logic;
		m_en : in std_logic;
		m_rw : in std_logic;
		mem_bus : inout std_logic_vector(n-1 downto 0)
	);
end entity memory;