library ieee;
use ieee.std_logic_1164.all;
entity reg_rst is
  port (
  d, 
  clk, 
  nrst : in std_logic;
  q : out std_logic
  );
end entity reg_rst;
 
architecture beh of reg_rst is
begin
process (clk, nrst) is
  begin
    if (nrst = '0') then
      q <= '0';
    elsif rising_edge(clk) then
      q <= d;
    end if;
  end process;
end architecture beh;