module signmult_tb();

reg [3:0] a,b;
wire [7:0] q;

signmult m1(q,a,b);

initial
  begin

    a = 4'b0000;
    b = 4'b0000;
    # 10 a = 4'b0110;
    # 10 b = 4'b0100;
    
    $display("a=%d b=%d q=%d\n", a, b, q);
  end

endmodule 