library ieee;
use ieee.std_logic_1164.all;
use work.processor_functions.all;
entity alu is
	port (
		clk : in std_logic;
		nrst : in std_logic;
		alu_cmd : in std_logic_vector(2 downto 0)	;
		alu_zero : out std_logic;
		alu_valid : in std_logic;	
		alu_bus : inout std_logic_vector(n-1 downto 0)
	);
end entity alu;