entity nrzi_decoder is
	port (
		clk : in std_logic;
		d : in std_logic;
		q : out std_logic
	);
end entity nrzi_decoder;

architecture basic of nrzi_decoder is
	signal lastd : std_logic := ‘0’;
begin
	p1 : process (clk)
	begin
		if rising_edge(clk) then
		if (d = lastd) then
			q <= ‘0’;
		else
			q <= ‘1’;
		end if;
		lastd <= d;
		end if;
	end process p1;
end architecture basic;