library ieee;
use ieee.std_logic_1164.all;

entity testram is
end entity testram;

architecture test of testram is
	signal address : integer range 0 to 2**8-1 := 0;
	signal rw : std_logic;
	signal c : std_logic;
	signal r : std_logic;
	signal data : std_logic_vector ( 15 downto 0 );
begin

	dram: entity work.dram1mb(behav) 
port map ( address, r, c, rw, data );
	address <= 23 after 0 ns, 47 after 30 ns, 23 after 90 ns;
	rw <= 	'0' after 0 ns, '1' after 90 ns;
	c <= 		'1' after 0 ns, '0' after 20 ns, 
'1' after 50 ns, '0' after 70 ns,
			'1' after 90 ns, '0' after 100 ns;
	r <= 		'1' after 0 ns, '0' after 10 ns, 
'1' after 40 ns, '0' after 60 ns,
			'1' after 80 ns, '0' after 100 ns;
	data <= 	X"1234" after 0 ns, X"5678" after 40 ns;
	
end architecture test;