architecture rtl of ir is

	signal ir_internal : std_logic_vector (n-1 downto 0);
begin
	ir_bus <= ir_internal 
when ir_valid = ‘1’ else (others => ‘z’);
	ir_opcode <= decode(ir_internal); 
	process (clk, nrst) is
	begin
		if nrst = ‘0’ then
			ir_internal <= (others => ‘0’);
		elsif rising_edge(clk) then
			if ir_load = ‘1’ then
				ir_internal <= ir_bus;
			end if;
		end if;
	end process;
end architecture rtl;