module dram1mbio ( address, row, col, rw, data );
  input [7:0] address; // Address
  input row;             // Row Selector
  input col;             // Column Selector
  input rw;              // Read/Write
  inout [15:0] data ;    // Data In

  wire [15:0] data;
  reg [15:0] dataout ;      // Data defined as a register
  
  reg [7:0] radd;    // Row Address
  reg [15:0] madd;   // Overall memory Address
  
  // define the memory array
  reg [15:0] memory [0:255]; // the memory array is 16 bits wide (data) and 2**8 -1 deep (address) 
  assign data = (rw) ? dataout : 16'hz;
  always @ (negedge row)
  begin
    radd = address;
  end
  
  always @ (negedge col)
  begin
    madd = radd*2**8 + address;
	  if(!rw) begin
	    memory[madd] <= data;
	  end
	  else begin
	    dataout <= memory[madd];
	  end	  
  end
endmodule
