library verilog;
use verilog.vl_types.all;
entity signmult is
    port(
        q               : out    vl_logic_vector(7 downto 0);
        a               : in     vl_logic_vector(3 downto 0);
        b               : in     vl_logic_vector(3 downto 0)
    );
end signmult;
