library verilog;
use verilog.vl_types.all;
entity alu is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        alu_op          : in     vl_logic_vector(7 downto 0);
        alu_zero        : out    vl_logic;
        alu_valid       : in     vl_logic;
        alu_bus         : inout  vl_logic_vector(15 downto 0)
    );
end alu;
