architecture rtl of controller is
	type states is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10);
	signal current_state, next_state : states;
begin
		state_sequence: process (clk, nrst) is
			if nrst = ‘0’ then
				current_state <= s0;
			else
				if rising_edge(clk) then
					current_state <= next_state;
				end if;
			end if;
		end process state_sequence;

		state_machine : process ( present_state, opcode ) is
-- state machine goes here
end process state_machine;
end architecture;