library ieee;
use ieee.std_logic_1164.all;  
use ieee.numeric_std.all;

entity twoscomplementtest is
end twoscomplementtest ;
 
architecture stimulus of twoscomplementtest is
	signal rst : std_logic := '0';
	signal clk : std_logic:='0';
   	signal count : std_logic_vector (7 downto 0);
   	signal inverse : std_logic_vector (7 downto 0);
   	signal check : std_logic_vector (7 downto 0);
	component twoscomplement 
		port(
			input : in std_logic_vector(7 downto 0);
			output : out std_logic_vector(7 downto 0)
		);
	end component;
	for all : twoscomplement use entity work.twoscomplement ;
begin
    CUT1: twoscomplement port map(input=>count,output=>inverse);
    CUT2: twoscomplement port map(input=>inverse,output=>check);

    -- clock and reset process
    clk <= not clk after 1 us;
    process
    begin
      rst<='0','1' after 2.5 us;
      wait; 
    end process;   

    -- generate data
    process(clk, rst)
      variable tempcount : unsigned(7 downto 0);
    begin
      if rst = '0' then
        tempcount := (others => '0');
      elsif rising_edge(clk) then
        tempcount := tempcount + 1;
      end if;
      count <= std_logic_vector(tempcount );
    end process;
end; 