library ieee;
use ieee.std_logic_1164.all;
entity vga is
	port (
		clk : in std_logic;
		nrst : in std_logic;
		hsync : out std_logic;
		vsync : out std_logic;
		red : out std_logic_vector ( 1 downto 0);
		green : out std_logic_vector ( 1 downto 0);
		blue : out std_logic_vector ( 1 downto 0);
		address : out (std_logic_vector ( 15 downto 0);
		data : in (std_logic_vector ( 7 downto 0);
		ram_en : out std_logic;
		ram_oe : out std_logic;
		ram_wr : out std_logic
	);
end entity vga;

architecture core of vga is

	--    vga internal signals go here

begin

	--  vga interface core goes here

end architecture core;