module zdelay (
  clk,  // clock input
  rst,	// reset input
  din,	// Digital Input
  dout	// Digital Output
  );
  
parameter n = 8;	// Width of Digital Input and Output

input clk;
input rst;
input [n-1:0]  din;
output [n-1:0] dout;

reg [n-1:0] dout;

reg [n-1:0] dstored;

always @ (posedge clk)
begin
	if (rst == 0 ) begin
	  dout <= 0;
	  dstored <= 0;
	end
	else begin
	  dout <= dstored;
	  dstored <= din;
	end
end

endmodule