library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity baudcontroller is
   	port(
			clk : in std_logic;   	
			rst :	in std_logic;	 
			baud  : in std_logic_vector(0 to 2);	
      		clkout : out std_logic;
end baudcontroller;

architecture simple of baudcontroller is
   	signal clkdiv : integer := 0;
		signal count : integer := 0;
begin
	div: process (rst, clk)
	begin
		if rst='0' then
			clkdiv <= 0;
			count <= 0;
		elsif rising_edge(clk) then
			case baud is
				when "000" => clkdiv <= 7; -- 115200
				when "001" => clkdiv <= 15; -- 57600
				when "010" => clkdiv <= 23; -- 38400
				when "011" => clkdiv <= 47; -- 19200
				when "100" => clkdiv <= 95; -- 9600
				when "101" => clkdiv <= 191; -- 4800
				when "110" => clkdiv <= 383; -- 2400
				when "111" => clkdiv <= 767; -- 1200
				when others => clkdiv <= 7; 
			end case;
		end if;
	end process; 

	clockdivision: process (clk, rst)
	begin
		if rst='0' then
			clkdiv <= 0;
			count <= 0;
		elsif rising_edge(clk) then
			count <= count + 1;
			if (count > clkdiv) then
				clkout <= not clkout;
				count <= 0;
			end if;
		end if;		
	end process;
end simple;