library ieee;
use ieee.std_logic_1164.all;
use work.processor_functions.all;
entity ir is
	port (
		clk : in std_logic;
		nrst : in std_logic;
		ir_load : in std_logic;
		ir_valid : in std_logic;
		ir_address : in std_logic;
		ir_opcode : out opcode;
		ir_bus : inout std_logic_vector(n-1 downto 0)
	);
end entity ir;