library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux41 is
  port (
    s : in std_logic_vector (1 downto 0);
    a : in std_logic;
    b : in std_logic;
    c : in std_logic;
    d : in std_logic;
    q : out std_logic
  );
end;

architecture simple of mux41 is
begin
  q <=  a when s = "00" else
        b when s = "01" else
        c when s = "10" else
        d when s = "11" else
        'X';
end;