
module dram1mbio_tb();
// declare the counter signals
reg row;
reg col;
reg rw;
reg [7:0] address;
wire [15:0] data;

reg [15:0] datain;

assign data = (!rw) ? datain : 16'hz;

// Set up the initial variables and reset
initial begin        
  $display ("time\t row col rw address data data_set");	
  $monitor ("%g\t %b   %b  %b %d %d %d", 
  $time, row, col, rw, address, datain, data);
  col = 1;       // set the col to 1
  rw = 1;        // set the rw to 1

  #1 address = 0;  // set the row to 1
  #1 datain = 23;
  #1 row = 0;  // set the row to 0
  #1 row = 1;  // set the row to 1
  #1 address = 1;  // set the row to 1
  #1 rw = 0;  // set the rw to 0   
  #1 col = 0;  // set the col to 0  
  #1 col = 1;  // set the col to 1 
  #1 rw = 1;  // set the rw to 1 
    
  // This should have written the data of 23 into location 0:1

  
  #1 address = 0;  // set the row to 1
  #1 datain = 47;  // set the data to 47
  #1 row = 0;  // set the row to 0
  #1 row = 1;  // set the row to 1
  #1 address = 2;  // set the row to 2
  #1 rw = 0;  // set the rw to 0  
  #1 col = 0;  // set the col to 0  
  #1 col = 1;  // set the col to 1    
  #1 rw = 1;  // set the rw to 1 
  
  // This should have written the data of 47 into location 0:2

  #1 address = 0;  // set the row to 1
  #1 row = 0;  // set the row to 0
  #1 row = 1;  // set the row to 1
  #1 address = 1;  // set the row to 1
  #1 col = 0;  // set the col to 0  
  #1 col = 1;  // set the col to 1      

  #100 $finish;      // Finish the  simulation
end

dram1mbio RAM ( address, row, col, rw, data);

endmodule
