library ieee;
use ieee.std_logic_1164.all;
entity pc is
	port (
		clk : in std_logic;
		nrst : in std_logic;
		pc_inc : in std_logic;
		pc_load : in std_logic;
		pc_valid : in std_logic;
		pc_bus : inout std_logic_vector(n-1 downto 0)
	);
end entity pc;