module shift_register (
  clk, 				// clock input
  rst,				// reset (active low)
  din,				// Digital Input
  shiftreg  		// shift register
  );

input clk;
input rst;
input din;

output [7:0] shiftreg;

wire clk;
wire rst;
wire din;

reg [7:0] shiftreg ;

always @ (posedge clk)
begin : count
  if (rst == 1'b0) begin
    shiftreg <=  #1  4'b00000000;
  end
  else begin
    shiftreg <=  #1  {din, shiftreg[7:1]};
  end
end

endmodule

