module manchester (
  clk,	// clock input
  d,	// data input
  q		// encoded output
);

input clk;
input d;

output q;
reg q;
reg lastd;

always_init begin
  lastd <= 0;
end

always @ (clk)
begin
  if clk='1' begin
    if d=1 then
    begin
    	q <= 1;
    	lastd <= 0;
    end
    else
	begin	
		q <= 0;
		lastd <= 1;
	end
  end
  else
  begin
  	if lastd = 0 then
  		q <= 0;
  	else
  		q = 1;
  	end
  end
endmodule
