module register (
  d,
  clk,
  nrst,
  load,
  q
  );
  
parameter n =8;

input [n-1:0] d;
input clk;
input nrst;
input load;

output q;
reg [n-1:0] q;

always @ (posedge clk or nrst)

if(nrst == 1b'0) then begin
  q <= 0;
end
else 
  if (load == 1b'1) then begin
    q <= d;
  end
end

endmodule
