library verilog;
use verilog.vl_types.all;
entity mar is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        mar_load        : in     vl_logic;
        mar_bus         : in     vl_logic_vector(15 downto 0);
        address         : out    vl_logic_vector(7 downto 0)
    );
end mar;
