library ieee;
use ieee.std_logic_1164.all;
entity latch is
  port (
    d :	in std_logic;
    en : in std_logic;
    q : out std_logic
    );
end entity latch;
 
architecture beh of latch is
begin
process (d, en) is
begin
  if (en = '1') then
    q <= d;
  end if;
end process;
end architecture beh;