library ieee;
use ieee.std_logic_1164.all;
entity dff_sr is
  port (	
    d : in std_logic;
    clk : in std_logic;
    nrst : std_logic;
    nset : in std_logic;
    q : out std_logic
  );
end entity dff_sr;
 
architecture simple of dff_sr is
begin
process (clk, nrst, nset) is
  begin
    if (nrst = '0') then
      q <= '0';
    elsif (nset = 1) then
      q <= '1';
    elsif rising_edge(clk) then
      q <= d;
    end if;
  end process;
end architecture beh;