library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sram is
  generic (
    m : natural := 16;
    n : natural := 16
  );
  port (
    clk : in std_logic;
	addr : in std_logic_vector (m-1 downto 0);
	wr : in std_logic;
    d : in std_logic_vector (n-1 downto 0);
	q : out std_logic_vector (n-1 downto 0)
  );
end entity sram;

architecture dualport of sram is
  type sramdata is array (0 to 2**m-1) of std_logic_vector (n-1 downto 0);
  signal memory : sramdata;
begin
  process (clk ) is
  begin
    if rising_edge(clk) then
      if wr = '0' then
        memory(to_integer(unsigned(addr))) <= d;
      else
        q <= memory(to_integer(unsigned(addr)));
      end if;
    end if;
  end process;
end architecture dualport;