module sram_verilog ( address, clk, rw, d, q );
  parameter m = 8;  // Address Bus Width
  parameter n = 16; // Data Bus Width
  input [m-1:0] address; // Address
  input clk;             // Clock
  input rw;              // Read/Write
  input [n-1:0] d ;    // Data In
  output [n-1:0] q ;  // Data Out

  wire [n-1:0] d;
  reg [n-1:0] q ;      // Data defined as a register
  
  
  // define the memory array
  reg [n-1:0] memory [0:2**m-1]; // the memory array is n bits wide (data) and 2**m -1 deep (address) 
  
  always @ (posedge clk)
  begin
	  if(!rw) begin
	    memory[address] <= d;
	  end
	  else begin
	    q <= memory[address];
	  end	  
  end
endmodule
