library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test1 is
  port (
    rst : in std_logic;
    clk : in std_logic;
    hexout : out std_logic_vector(6 downto 0)
  );
end test1;
 
architecture stimulus of test1 is
  signal charin : std_logic_vector(3 downto 0);

  component hexdecoder 
    port(
      charin : in std_logic_vector(3 downto 0);
      hexout : out std_logic_vector(6 downto 0)
    );
  end component;
  for all : hexdecoder use entity work.hexdecoder ;
	
begin

  CUT: hexdecoder port map(charin => charin, hexout => hexout);

  process(clk, rst)
    variable count : unsigned(26 downto 0);
	variable charcount : unsigned(3 downto 0);
  begin
    if rst = '0' then
      count := (others => '0');
      charcount := (others => '0');
    elsif rising_edge(clk) then
      if count = 50000000 then
        count := (others => '0');
        charcount := charcount + 1;
      else
        count := count + 1;
      end if;
    end if;
    charin <= std_logic_vector(charcount);
  end process;
end;      