library verilog;
use verilog.vl_types.all;
entity zgain is
    generic(
        n               : integer := 8;
        gain            : integer := 1
    );
    port(
        din             : in     vl_logic_vector;
        dout            : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of n : constant is 1;
    attribute mti_svvh_generic_type of gain : constant is 1;
end zgain;
