library ieee;
use ieee.std_logic_1664.all;

entity manchester_encoder is
	port (
		clk : in std_logic;
		d : in std_logic;
		q : out std_logic
	);
end entity manchester_encoder;

architecture basic of manchester_encoder is
	signal lastd : std_logic := ‘0’;
begin
	p1: process ( clk )
	begin
		if  clk'event and clk='1' then
			if ( d = ‘0’ ) then
				q <= ‘1’;
				lastd <= ‘0’;
			elsif ( d = ‘1’ ) then
				q <= ‘0’;
				lastd <= ‘1’;
			else
				q <= ‘x’;
				lastd <= ‘x’;
			end if;
		else
			if ( lastd = ‘0’ ) then
				q <= ‘0’;
			elsif ( lastd = ‘1’ ) then
				q <= ‘1’;
			else
				q <= ‘x’;
			end if
		end if;				
	end process p1;
end architecture basic;