module nrzi_encoder (
	clk,	// CLock Input
	d,		// Data Input
	q 		//	Data Output
	);
	
input clk;
input d;
output q;

reg q;

reg qint;

always_init
begin
	qint <= 0;
end

always @ (clk)
begin
	if d=1
		if qint = 0
			qint <= 1
		else
			qint <= 0
		end
	
	end
	q <= qint;
end
endmodule
