entity flash is
  generic (
    a : natural := 10;
    d : natural := 8
  );
  port (
    clk : in std_logic;
    addr : in std_logic_vector(a-1 downto 0);
    data : inout std_logic_vector (d-1 downto 0);
    cle : in std_logic;
    ale : in std_logic;
    ce : in std_logic;
    re : in std_logic;
    we : in std_logic;
    wp : in std_logic;
    busy : out std_logic;
);
end entity flash;