
module sram_verilog_tb();
// declare the counter signals
parameter m = 8;
parameter n = 16;
reg rw;
reg clk;
reg [m-1:0] address;
wire [n-1:0] dataout;

reg [n-1:0] datain;

// Set up the initial variables and reset
initial begin        
  $display ("time\t rw address data data_set");	
  $monitor ("%g\t  %b %d %d %d", 
  $time, rw, address, datain, dataout);	
  rw = 1;        // set the rw to 1
  clk = 0;       // INit the clk to 0
  
  #10 address = 0;  // set the row to 1
  #10 datain = 23;
  #10 rw = 0;  // set the rw to 0   
  #10 address = 1;  // set the row to 1

  #10 rw = 1;  // set the rw to 1 
    
  // This should have written the data of 23 into location 0:1

  
  #10 address = 0;  // set the row to 1
  #10 datain = 47;  // set the data to 47
  #10 address = 2;  // set the row to 2
  #10 rw = 0;  // set the rw to 0   
  #10 rw = 1;  // set the rw to 1 
  
  // This should have written the data of 47 into location 0:2

  #10 address = 0;  // set the row to 1
  #10 address = 1;  // set the row to 1
   

  #100 $finish;      // Finish the  simulation
end

// Clock
always begin
  #5  clk = ~clk; // Invert the clock every 5 time ticks
end

sram_verilog RAM ( address, clk, rw, datain, dataout);

endmodule
