		state_machine : process ( present_state, opcode ) is
		begin
			-- reset all the control signals
			ir_load <= ‚äò0‚äô;
			ir_valid <= ‚äò0‚äô;
			ir_address <= ‚äò0‚äô;
			pc_inc <= ‚äò0‚äô;
			pc_load <= ‚äò0‚äô;
			pc_valid <= ‚äò0‚äô;
			mdr_load <= ‚äò0‚äô;
			mar_load <= ‚äò0‚äô;
			mar_valid <= ‚äò0‚äô;
			m_en <= ‚äò0‚äô;
			m_rw <= ‚äò0‚äô;
			case current_state is
			  when s0 =>
				pc_valid<=‚äô1‚äô; 
				mar_load<=‚äô1‚äô; 
				pc_inc<=‚äô1‚äô; 
				pc_load<=‚äô1‚äô;
				next_state<=s1;
			  when s1 =>
				m_en<=‚äô1‚äô; 
				m_rw<=‚äô1‚äô; 
				next_state<=s2;
			  when s2 =>
				mdr_valid<=‚äô1‚äô; 
				ir_load<=‚äô1‚äô; 
				next_state<=s3;
			  when s3 =>										
				mar_load<=‚äô1‚äô; 
				ir_address<=‚äô1‚äô; 
				if opcode = store then 
					next_state<=s4; 
				else 
					next_state <=s6;
				end if;
			  when s4 =>
				mdr_load<=‚äô1‚äô; 
				acc_valid<=‚äô1‚äô; 
				next_state<=s5;
			  when s5 =>
				m_en <= ‚äò1‚äô;
				next_state <= s0;
			  when s6 =>
				m_en<=‚äô1‚äô; m_rw<=‚äô1‚äô; 
				if opcode = load then 
					next_state<=s7; 
				else 
					next_state <=s8;
				end if;
			  when s7 =>
				mdr_valid<=‚äô1‚äô; 
				acc_load<=‚äô1‚äô; 
				next_state<=s0;
			  when s8 =>
				m_en<=‚äô1‚äô; 
				m_rw<=‚äô1‚äô; 
				if opcode = add then 
					next_state<=s9; 
				else 
					next_state <=s10;
				end if;
			  when s9 =>
				alu_add <= ‚äò1‚äô; 
				next_state<=s0;
			  when s10 =>
				alu_sub <= ‚äò1‚äô;
				next_state<=s0;
			end case;
end process state_machine;