module counter (
clk,	// Clock Signal (Rising Edge)
rst,	// reset Signal (Active High)
dout	// Counter Output (7:0)
);
// port declarations
input clk;
input rst;
output [7:0] dout;

// wire definitions
wire clk;
wire rst;

// Register definitions
reg [7:0] dout;

always @ ( posedge clk )	// Count on the Rising Edge of the Clock
begin: COUNTER // Start of the Counter - block name COUNTER

	if (rst == 1'b1) begin
		dout <=  #1  8'b00000000;
	end
	else begin
		dout <=  #1  dout + 1;
	end

end // End of the Counter - end of block COUNTER

endmodule