Architecture dualport of sram is
	Type sramdata is array (0 to 2**m-1) of
		Std_logic_vector (n-1 downto 0);
	Signal memory : sramdata;
Begin
	Process (clk ) is
	Begin
		If rising_edge(clk) then
			If wr = ‘0’ then
				Memory(to_integer(unsigned(addr))) <= d;
			Else
				Q <= memory(to_integer(unsigned(addr)));
			End if;
		End if;
	End process;
End architecture dualport;