library ieee;
use ieee.std_logic_1164.all;

entity fsm is
  port(
    clk, rst, choice : in std_logic;
    count : out std_logic
  );
end entity fsm;
architecture simple of fsm1 is
	type state_type is ( s0, s1, s2, s3 );
	signal current, next_state : state_type;
begin
  process ( clk )
  begin
    if ( clk = 1 ) then
      current <= next_state;
    end if;
  end process;

  process ( current )
  begin
    case current is
      when s0 =>
        out <= 0;
        if ( rst = 1) then
          next <= s1;
        else
          next <= s0;
        end if;
      when s1=>
        out <= 1;
        if ( choice = 1) then
          next <= s3;
        else
          next <= s2;
        end if;
      when s2=>
        out <= 2;
        next <= s0;
      when s3=>
        out <= 3;
        next <= s0;
    end case;
  end process;
end;