architecture behav of dram1mb is
begin
process (raddr, caddr, rw) is
  type dram is array (0 to 2**16 - 1) of std_logic_vector(15 downto 0);
  variable radd: INTEGER range 0 to 2**8 - 1;
  variable madd: INTEGER range 0 to 2**16 - 1;
  variable memory: dram;
begin
  data <= (others => 'Z');
  if falling_edge(raddr) then
    radd := address;
  elsif falling_edge(caddr) then
    madd:=radd*2**18 +Address;
    if raddr = '0' and rw = '0' then
      memory(madd) := data;
    end if;
  elsif caddr = '0' and raddr = '0' and rw = '1' then
    data <= memory(madd);
  end if;
end process;
end architecture behav;