module dram1mb ( address, row, col, rw, datain, dataout );

  input [7:0] address; // Address
  input row;             // Row Selector
  input col;             // Column Selector
  input rw;              // Read/Write
  input [15:0] datain ;    // Data In
  output [15:0] dataout ;  // Data Out

  wire [15:0] datain;
  reg [15:0] dataout ;      // Data defined as a register
  
  reg [7:0] radd;    // Row Address
  reg [15:0] madd;   // Overall memory Address
  
  // define the memory array
  reg [15:0] memory [0:255]; // the memory array is 16 bits wide (data) and 2**8 -1 deep (address) 
  
  always @ (negedge row)
  begin
    radd = address;
  end
  
  always @ (negedge col)
  begin
    madd = radd*2**8 + address;
	  if(!rw) begin
	    memory[madd] <= datain;
	  end
	  else begin
	    dataout <= memory[madd];
	  end	  
  end
endmodule
