library ieee;
use ieee.std_logic_1164.all;
entity register is
  generic (
    n : natural := 8
  );
  port (
    d : in std_logic_vector(n-1 downto 1);
    clk : in std_logic;
    nrst : in std_logic;
    load : in std_logic;
    q : out std_logic_vector(n-1 downto 1)
  );
end entity register;

architecture beh of register is
begin
process (clk, nrst) is
  begin
    if (nrst = '0') then
      q <= (others => '0');
    elsif (rising_edge(Clock) and (load = ‘1’)) then
      q <= d;
    end if;
  end process;
end architecture beh;