library ieee;
use ieee.std_logic_1164.all;

entity ROM16x8_TB is
end entity ROM16x8_TB;

architecture TB of ROM16x8_TB is
	signal address : integer := 0;
	signal data : std_logic_vector ( 7 downto 0 );
begin
	ROM16x8: entity work.ROM16x8(example) 
port map ( address, data );
end architecture TB;