library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Decoder38Test is
end Decoder38Test;
 
architecture stimulus of Decoder38Test is
	signal rst : std_logic := '0';
	signal clk : std_logic:='0';
	signal s : std_logic_vector(2 downto 0);
	signal q : std_logic_vector(7 downto 0);

	component decoder38 
		port(
			s : in std_logic_vector(2 downto 0);
			q : out std_logic_vector(7 downto 0)
		);
	end component;
	for all : decoder38 use entity work.decoder38 ;
	
begin

    CUT: decoder38 port map(s => s, q => q);
    clk <= not clk after 1 us;
    process
    begin
      rst<='0','1' after 2.5 us;
      wait; 
    end process;  

  process(clk, rst)
    variable count : unsigned(2 downto 0);
  begin
    if rst = '0' then
      count := (others => '0');
    elsif rising_edge(clk) then
      count := count + 1;
    end if;
    s <= std_logic_vector(count);
  end process;

end;      