module zdiff (
  din1,	// Digital Input 1
  din2,	// Digital Input 2
  dout	// Digital Output
  );
  
parameter n = 8;	// Width of Digital Input and Output

input [n-1:0]  din1;
input [n-1:0]  din2;
output [2*n-1:0] dout;

wire signed [n-1:0] din1;
wire signed [n-1:0] din2;
reg signed [2*n-1:0] dout;

always @ (din1 or din2)
begin
	dout <= din1 - din2;
end

endmodule