library ieee;
use ieee.std_logic_1164.all;
entity n_inverter is
  generic (
    n : natural := 16
  );
  port (
    a : in std_logic_vector((n-1) downto 0);
    q : out std_logic_vector((n-1) downto 0)
	);
end entity n_inverter;
architecture simple of n_inverter is
begin
  q <= not a;
end architecture simple;