`define N 8

module busif (clk,nrst,oen,data);

input clk;
input nrst;
input oen;

inout [`N-1:0] data;

wire [`N-1:0] data;

reg [`N-1:0] counter;



always @(posedge clk) begin
  if(nrst==0) begin
    counter <= 0;
  else begin
    counter <= counter + 1;
  end
end

endmodule