entity manchester_decoder is
	port (
		clk : in std_logic;
		d : in std_logic;
		q : out std_logic
	);
end entity manchester_decoder;

architecture basic of manchester_decoder is
	signal lastd : std_logic := ‘0’;
begin
	p1 : process (clk)
	begin
		if clk'event and clk='1' then
			lastd <= d;
		else
			if (lastd = ‘0’) and (d = ‘1’) then
				q <= ‘1’;
			elsif (lastd = ‘1’) and (d=’0’) then
				q <= ‘0’;
			else
				q <= ‘x’;
			end if;
		end if;
	end process p1;
end architecture basic;