library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testram is
end entity testram;

architecture test of testram is
	signal address : std_logic_vector ( 7 downto 0 );
	signal clk : std_logic;
	signal wr : std_logic;
	signal d : std_logic_vector ( 15 downto 0 );
	signal q : std_logic_vector ( 15 downto 0 );
	constant period : time := 5 ns;
begin

sram: entity work.sram(dualport)  generic map ( 8, 16) port map ( clk, address, wr, d, q ) ;

address <= "00000001" after 0 ns, "00000010" after 30 ns, "00000001" after 90 ns;
wr <= 	'0' after 0 ns, '1' after 90 ns;
d <= 	X"1234" after 0 ns, X"5678" after 40 ns;


 -- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
  clk <= '0';
  wait for period/2; 
  clk <= '1';
  wait for period/2;
end process;
   
end architecture test;