module bcd_counter (
  clk, 				// clock input
  rst,				// reset (active low)
  counter_output  	// counter output
  );

input clk;
input rst;

output [3:0] counter_output;

wire clk;
wire rst;

reg [3:0] counter_output ;

always @ (posedge clk)
begin : count
  if (rst == 1'b0) begin
    counter_output <=  #1  4'b0000;
  end
  else begin
    if(counter_output < 9) begin
      counter_output <=  #1  counter_output + 1;
	end
	else
	  counter_output <= #1  4'b0000;
  end
end

endmodule

