library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity serialrx is
   	port(
			clk : in std_logic;   	
			rst :	in std_logic;	 
			rx  : in std_logic;	
      		dout : out std_logic_vector (7 downto 0)
      		);
end serialrx;

architecture simple of serialrx is
  type state is (idle, s0, s1, s2, s3, s4, s5, s6, s7, stop);
  signal current_state, next_state : state;
  signal databuffer : std_logic_vector(7 downto 0);
begin
receive: process (rst, clk)
begin
if rst='0' then
			current_state  <= idle;
			for i in 7 downto 0 loop
				dout(i) <= '0';
			end loop;
elsif rising_edge(clk) then

     			case current_state is
       		when idle =>
         		if rx = '0' then 
           			next_state <= s0;
         		else
           			next_state <= idle;
      			end if;
	when s0 => 
next_state <= s1;
databuffer(0) <= rx;
	when s1 => 
next_state <= s2;
databuffer(1) <= rx;
	when s2 => 
next_state <= s3;
databuffer(2) <= rx;
	when s3 => 
next_state <= s4;
databuffer(3) <= rx;
	when s4 => 
next_state <= s5;
databuffer(4) <= rx;
	when s5 => 
next_state <= s6;
databuffer(5) <= rx;
	when s6 => 
next_state <= s7;
databuffer(6) <= rx;
	when s7 => 
next_state <= stop;
databuffer(7) <= rx;
       		when stop =>
         			if rx = '0' then 
           				next_state <= s0;
         			else
           				next_state <= idle;
      				end if;
				dout <= databuffer;
end case;
current_state <= next_state;
end if;
end process;
end;