library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dram1mb is
  port (
    address : in integer range 0 to 2**8-1;  -- Row Address
    row : in std_logic;  -- Row Select
    col : in std_logic;  -- Column Select
    rw : std_logic; -- Read/Write
    data : inout std_logic_vector (15 downto 0) -- Data
  );
end entity dram1mb;

architecture behav of dram1mb is
begin
process (row, col, rw) is
  type dram is array (0 to 2**16 - 1) of std_logic_vector(15 downto 0);
  variable radd: INTEGER range 0 to 2**8 - 1;
  variable madd: INTEGER range 0 to 2**16 - 1;
  variable memory: dram;
begin
  data <= (others => 'Z');
  if falling_edge(row) then
    radd := address;
  elsif falling_edge(col) then
    madd :=radd*2**8 +address;
    if row = '0' and rw = '0' then
      memory(madd) := data;
    end if;
  elsif col = '0' and row = '0' and rw = '1' then
    data <= memory(madd);
  end if;
end process;
end architecture behav;