library ieee;
use ieee.std_logic_1164.all;
entity alu_logic is
	generic (
		n : natural := 16
	);
	port (
		a : in std_logic_vector((n-1) downto 0);
		b : in std_logic_vector((n-1) downto 0);
		s : in std_logic_vector(1 downto 0);
		q : out std_logic_vector((n-1) downto 0)
	);
end entity alu_logic;