module nrzi_encoder (
	clk,	// CLock Input
	d,		// Data Input
	q 		//	Data Output
	);
	
input clk;
input d;
output q;

reg q;

always @ (clk)
begin
	if clk=1 begin
		if d=lastd 
			q <= 0;
		else
			q <= 1;
		end
	end
end
endmodule