library verilog;
use verilog.vl_types.all;
entity pc is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        pc_inc          : in     vl_logic;
        pc_valid        : in     vl_logic;
        pc_load         : in     vl_logic;
        data            : inout  vl_logic_vector(7 downto 0)
    );
end pc;
