`define N 8


module busif_tb();
// declare the counter signals
reg clk;
reg nrst;
reg oen;
wire [`N-1:0] databus;

// Set up the initial variables and reset
initial begin        
  $display ("time\t clk reset oen data");	
  $monitor ("%g\t %b   %b  %b %b", 
  $time, clk, nrst, oen, databus);	
  clk = 1;       // initialize the clock to 1
  nrst = 1;       // set the reset to 1 (not reset)
  oen = 0;
  #5 nrst = 0;    // reset = 0 : resets the counter
  #10 nrst = 1;   // reset back to 1 : counter can start
  #30 oen = 1;    // reset = 0 : resets the counter
  #50 oen = 0;   // reset back to 1 : counter can start
  #100 $finish;      // Finish the  simulation
end

// Clock generator
always begin
  #5 clk = ~clk; // Clock every 5 time slots
end

// Connect DUT to test bench
busif DUT (
clk,
nrst,
oen,
databus
);

endmodule