
module fsm_tb();
// declare the counter signals
reg clk;
reg rst;
reg choice;
wire [1:0] counter_output;

// Set up the initial variables and reset
initial begin        
  $display ("time\t clk reset choice counter");	
  $monitor ("%g\t %b   %b  %b %b", 
  $time, clk, rst, choice, counter_output);	
  clk = 1;       // initialize the clock to 1
  rst = 1;       // set the reset to 1 (not reset)
  choice = 0;    // set the choice to 0
  #5 rst = 0;    // reset = 0 : resets the counter
  #10 rst = 1;   // reset back to 1 : counter can start
  #30 choice = 1;   // change the choice to 1 
  #100 $finish;      // Finish the  simulation
end

// Clock generator
always begin
  #5 clk = ~clk; // Clock every 5 time slots
end

// Connect DUT to test bench
fsm DUT (counter_output,clk,rst,choice);

endmodule