library verilog;
use verilog.vl_types.all;
entity ir is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        ir_valid        : in     vl_logic;
        ir_load         : in     vl_logic;
        ir_bus          : inout  vl_logic_vector(15 downto 0)
    );
end ir;
