module zdelay_tb();
// declare the counter signals
reg clk;
reg signed [7:0] zvalue;
reg rst;

wire signed [7:0] gvalue;
// Set up the initial variables and reset
initial begin        
  $display ("time\t clk zvalue");	
  $monitor ("%g\t %b   %d", 
  $time, clk, zvalue);	
  clk = 1;       // initialize the clock to 1
  rst = 1;       // set the reset to 1 (not reset)
  #5 rst = 0;    // reset = 0 : resets the counter
  #10 rst = 1;   // reset back to 1 : counter can start
  #10 zvalue = 23;
  #10 zvalue = 54;
  #10 zvalue = 12;   
  #1000 $finish;      // Finish the  simulation
end

// Clock generator
always begin
  #5 clk = ~clk; // Clock every 5 time slots
end
	
zdelay #(8) a1(clk, rst, zvalue, gvalue);

endmodule