
\begin{verbatim}
ENTITY SRAM IS
  GENERIC (
	M : natural := 10;
	N : natural := 8
	);
  PORT (
	clk : in std_logic;
addr : in std_logic_vector(m-1 downto 0);
	wr : in std_logic;
      d : in std_logic_vector (n-1 downto 0);
	q : out std_logic_vector (n-1 downto 0)
);
END ENTITY SRAM;
\end{verbatim}