
module johnson_counter_tb();
// declare the signals
reg clk;
reg rst;
reg din;
wire [7:0] johnson_counter_values;

// Set up the initial variables and reset
initial begin        
  $display ("time\t clk reset counter");	
  $monitor ("%g\t %b   %b 	%h", 
  $time, clk, rst, johnson_counter_values);	
  clk = 1;       // initialize the clock to 1
  rst = 1;       // set the reset to 1 (not reset)
  #5 rst = 0;    // reset = 0 : resets the counter
  #10 rst = 1;   // reset back to 1 : counter can start
  #1000 $finish;      // Finish the  simulation
end

// Clock generator
always begin
  #5 clk = ~clk; // Clock every 5 time slots
end

// Connect DUT to test bench
johnson_counter DUT (
clk,
rst,
johnson_counter_values
);

endmodule