entity four_bit_adder is
  port (sum: out bit_vector (3 downto 0);  co : out bit;
        a, b : in bit_vector (3 downto 0); ci : in bit);
end entity four_bit_adder;

architecture simple of four_bit_adder is
  signal carry : bit_vector (3 downto 1);
begin
  fa0 : entity work.full_adder 
port map (sum(0),carry(1),a(0),b(0),ci);
  fa1 : entity work.full_adder 
port map (sum(1),carry(2),a(1),b(1),carry(1));
  fa2 : entity work.full_adder 
port map (sum(2),carry(3),a(2),b(2),carry(2));
  fa3 : entity work.full_adder 
port map (sum(3),co,a(3),b(3),carry(3));
end architecture simple;