library verilog;
use verilog.vl_types.all;
entity mdr is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        mdr_load        : in     vl_logic;
        mdr_valid       : in     vl_logic;
        mem_bus         : in     vl_logic_vector(15 downto 0);
        mdr_bus         : inout  vl_logic_vector(15 downto 0)
    );
end mdr;
