library ieee;
use ieee.std_logic_1164.all;
entity testAES is
end;


library ieee;
use ieee.std_logic_1164.all;
use work.aes_functions.all;
architecture behaviour of testAES is

	component aes
		port(
			plaintext : in std_logic_vector(127 downto 0);
			keytext :	in std_logic_vector(127 downto 0);
			encrypt : in std_logic;
			go : in std_logic;
			ciphertext : out std_logic_vector(127 downto 0);
			done : out std_logic
		);
	end component;

	for all : aes use entity work.aes;

	signal plaintext : std_logic_vector(127 downto 0);
	signal keytext :	std_logic_vector(127 downto 0);
	signal encrypt : std_logic;
	signal go : std_logic := '0';
	signal ciphertext : std_logic_vector(127 downto 0);
	signal done : std_logic; 
	signal ok : std_logic := '0';
begin
	plaintext <= 	X"00000000000000000000000000000000", X"3243f6a8885a308d313198a2e0370734" after 50 ns ;
	keytext <= 	X"00000000000000000000000000000000", X"2b7e151628aed2a6abf7158809cf4f3c" after 100 ns;


	process (ciphertext)
	    		variable ct : std_logic_vector(127 downto 0) := X"3925841d02dc09fbdc118597196a0b32";
	begin
	    assert ct = ciphertext
			report "Test vectors do not match"
		severity note;
	    assert not (ct = ciphertext)
			report "Test vectors Matched"
			severity note;
	end process;


	process
	begin
		go <= not go after 20 ns;
	end process;

	DUT : aes port map (plaintext, keytext, encrypt, go, ciphertext, done);
end;