library ieee;
use ieee.std_logic_1164.all;

entity psmouse is
	port (
		clock : in std_logic;
		data : in std_logic
	);
end entity psmouse;

architecture basic of psmouse is
	signal d : std_logic_vector (23 downto 0);
	signal byte1 : std_logic_vector (7 downto 0);
	signal byte2 : std_logic_vector (7 downto 0);
	signal byte3 : std_logic_vector (7 downto 0);
	signal index : integer := 23;
begin
	process(clock) is
	begin
		if falling_edge(clock) then
			d(index) <= data;
			if index>0 then
				index <= index-1;
			else
				byte1 <= d(23 downto 16);
				byte2 <= d(15 downto 8);
				byte3 <= d(7 downto 0);
				index<=23;
			end if;
		end if;
	end process;
end architecture basic;