library ieee;
use ieee.std_logic_1164.all;
entity DES is
  port ( 
    plaintext : in std_logic_vector(1 to 64);
    key : in std_logic_vector(1 to 64);
    encrypt : in std_logic;
    go : in std_logic;
    ciphertext : out std_logic_vector(1 to 64);
    done : out std_logic
  );
end;

architecture behavior of DES is
  subtype vec56 is std_logic_vector(1 to 56);
  ...
  subtype vec64 is std_logic_vector(1 to 64);
begin
  process
  begin
    wait until go = ’1’;
    done <= ’0’;
    wait for 0 ns;
    ciphertext <=
    des_core(plaintext, key_reduce(key), encrypt);
    done <= ’1’;
  end process;
end;