module johnson_counter (
  clk, 				// clock input
  rst,				// reset (active low)
  johnsonreg  		// shift register
  );

input clk;
input rst;

output [7:0] johnsonreg;

wire clk;
wire rst;

reg [7:0] johnsonreg ;

always @ (posedge clk)
begin : count
  if (rst == 1'b0) begin
    johnsonreg <=  #1  4'b00000000;
  end
  else begin
    johnsonreg <=  #1  {!johnsonreg[0], johnsonreg[7:1]};
  end
end

endmodule

