library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
  generic (
	 n : integer := 4;
  port (
        clk : in std_logic;
        rst : in std_logic;
	  din : in std_logic;
        q : out std_logic_vector((n-1) downto 0)
  );
end entity;

architecture simple of shift_register is
begin
  process(clk, rst)
    variable shift_reg : std_logic_vector((n-1) downto 0);
  begin
    if rst = '0' then
      shift_reg := (others => ‘0’);
    elsif rising_edge(clk) then
      shift_reg := shift_reg(n-2 downto 0) & din;
    end if;
    q <= shift_reg;
  end process;
end architecture simple;