library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux21 is
  port (
    s : in std_logic;
    a : in std_logic;
    b : in std_logic;
    q : out std_logic
  );
end;

architecture simple of mux21 is
begin
  q <=  a when s = '0' else
        b when s = '1' else
        'X';
end;