entity counter is
   port (
      clk : IN std_logic ;
      rst : IN std_logic ;
      output : OUT std_logic_vector (3 DOWNTO 0)) ;
end counter ;

architecture simple of counter is
   signal clk_int, rst_int, output_dup0_3, output_dup0_2, output_dup0_1, 
      output_dup0_0, output_nx4, output_nx7, output_nx10, NOT_rst, 
      output_NOT_a_0: std_logic ;

begin
   output_obuf_0 : OBUF port map ( O=>output(0), I=>output_dup0_0);
   output_obuf_1 : OBUF port map ( O=>output(1), I=>output_dup0_1);
   output_obuf_2 : OBUF port map ( O=>output(2), I=>output_dup0_2);
   output_obuf_3 : OBUF port map ( O=>output(3), I=>output_dup0_3);
   rst_ibuf : IBUF port map ( O=>rst_int, I=>rst);
   output_3_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_3, D=>output_nx4, 
      C=>clk_int, CLR=>NOT_rst);
   output_2_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_2, D=>output_nx7, 
      C=>clk_int, CLR=>NOT_rst);
   output_1_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_1, D=>output_nx10, 
      C=>clk_int, CLR=>NOT_rst);
   output_0_EXMPLR_EXMPLR : FDC port map ( Q=>output_dup0_0, D=>
      output_NOT_a_0, C=>clk_int, CLR=>NOT_rst);
   clk_ibuf : BUFGP port map ( O=>clk_int, I=>clk);
   output_nx4 <= (not output_dup0_3 and output_dup0_2 and output_dup0_1 and 
   output_dup0_0) or (output_dup0_3 and not output_dup0_0) or (output_dup0_3
    and not output_dup0_2) or (output_dup0_3 and not output_dup0_1) ;
   output_nx7 <= (output_dup0_2 and not output_dup0_0) or (not output_dup0_2
    and output_dup0_1 and output_dup0_0) or (output_dup0_2 and not 
   output_dup0_1) ;
   output_nx10 <= (output_dup0_0 and not output_dup0_1) or (not 
   output_dup0_0 and output_dup0_1) ;
   NOT_rst <= (not rst_int) ;
   output_NOT_a_0 <= (not output_dup0_0) ;
end simple ;