entity nrzi_encoder is
	port (
		clk : in std_logic;
		d : in std_logic;
		q : out std_logic
	);
end entity nrzi_encoder;

architecture basic of nrzi_encoder is
	signal qint : std_logic := ‘0’;
begin
	p1 : process (clk)
	begin
		if (d = ‘1’) then
			if ( qint = ‘0’ ) then
				qint <= ‘1’;
			else
				qint <= ‘0’;
			end if;
		end if;
	end process p1;
	q <= qint;
end architecture basic;