library ieee;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity mult_sign is
  generic(top : natural := 15);
    port (
	  clk : in std_logic;
	  nrst : in std_logic;
	  a    : in  std_logic_vector (top downto 0);
          b    : in  std_logic_vector (top downto 0);
          product  : out std_logic_vector (2*top+1 downto 0)
          );
end entity mult_sign;

architecture behavior of mult_sign is
begin
	p1 : process (a,b)
	begin
		product <= std_logic_vector(signed(a) * signed(b));
	end process p1;
end architecture behavior;