library IEEE;
use IEEE.std_logic_1164.all;

entity add_beh is
  generic(top : natural := 15);
    port (
      a    : in  std_logic_vector (top downto 0);
      b    : in  std_logic_vector (top downto 0);
      cin  : in  std_logic;
      sum  : out std_logic_vector (top downto 0);
      cout : out std_logic
    );
end entity add_beh;